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? 2009-2014 microchip technology inc. ds20002197c-page 1 mcp631/2/3/4/5/9 features: ? gain-bandwidth product: 24 mhz ? slew rate: 10 v/s ? noise: 10 nv/ ? hz at 1 mhz) ? low input bias current: 4 pa (typical) ? ease of use: - unity-gain stable - rail-to-rail output - input range including negative rail - no phase reversal ? supply voltage range: +2.5v to +5.5v ? high output current: 70 ma ? supply current: 2.5 ma/ch (typical) ? low-power mode: 1 a/ch ? small packages: sot23-5, dfn ? extended temperature range: -40c to +125c typical applications: ? fast low-side current sensing ? point-of-load control loops ? power amplifier control loops ? barcode scanners ? optical detector amplifier ? multi-pole active filter design aids: ? spice macro models ?filterlab ? software ? microchip advanced part selector (maps) ? analog demonstration and evaluation boards ? application notes description: the microchip technology inc. mcp631/2/3/4/5/9 family of operational amplifiers features high gain bandwidth product (24 mhz, typical) and high output short-circuit current (70 ma, typical). some also provide a chip select (cs ) pin that supports a low-power mode of operation. these amplifiers are optimized for high speed, low noise and distortion, single-supply operation with rail-to-rail output and an input that includes the negative rail. this family is offered in single (mcp631), single with cs pin (mcp633), dual (mcp632), dual with two c s pins (mcp635), quad (mcp634) and quad with two chip select pins (mcp639). all devices are fully specified from -40c to +125c. typical application circuit v out 0a ? 20 a mcp63x 0.005 ? 51.1 ? 51.1 ? 2.0 k ? +5v 0v ? 4v + - high gain-bandwidth op amp portfolio model family channels/package gain-bandwidth v os (max.) i q /ch (typ.) mcp621/1s/2/3/4/5/9 1, 2, 4 20 mhz 0.2 mv 2.5 ma mcp631/2/3/4/5/9 1, 2, 4 24 mhz 8.0 mv 2.5 ma mcp651/1s/2/3/4/5/9 1, 2, 4 50 mhz 0.2 mv 6.0 ma mcp660/1/2/3/4/5/9 1, 2, 3, 4 60 mhz 8.0 mv 6.0 ma 24 mhz, 2.5 ma rail-to-rail output (rro) op amps
mcp631/2/3/4/5/9 ds20002197c-page 2 ? 2009-2014 microchip technology inc. package types mcp631 soic mcp632 soic v in + v in ? v ss v dd v out 1 2 3 4 8 7 6 5 nc nc nc v ina + v ina ? v ss 1 2 3 4 8 7 6 5 v outa v dd v outb v inb - v inb + mcp635 msop v ina + v ina ? v ss 1 2 3 4 10 9 8 7 v outa v dd v outb v inb - v inb + cs a 5 6 cs b mcp632 3x3 dfn* v ina + v ina ? v ss v outa v dd v outb v inb ? v inb + * includes exposed thermal pad (ep); see tab l e 3 - 1 . 1 2 3 4 8 7 6 5 mcp633 soic v in + v in ? v ss v dd v out 1 2 3 4 8 7 6 5 nc cs nc mcp634 soic, tssop v ina + v ina - v dd 1 2 3 4 14 13 12 11 v outa v outd v ind - v ind + v ss v inb + 5 10 v inc + v inb - 6 9 v outb 7 8 v outc v inc - 2 v dd v inb + v ina - v ind + v ss v inb - v inc + v outb cs bc v outc v inc - v outa cs ad v outd v ind - v ina + ep 16 1 15 14 13 3 4 12 11 10 9 5678 17 mcp639 4x4 qfn* ep 9 mcp631 2x3 tdfn* v in + v in ? v ss v dd v out 1 2 3 4 8 7 6 5 nc nc nc ep 9 v in + v out v ss v in - mcp631 sot-23-5 v dd 1 2 3 4 5 cs v in + v out v ss v in - mcp633 sot-23-6 v dd 1 2 3 4 5 6 mcp635 3x3 dfn* v ina + v ina ? cs a v outa v dd v outb v inb - cs b 1 2 3 5 10 9 8 6 v ss v inb + 4 7 ep 11
? 2009-2014 microchip technology inc. ds20002197c-page 3 mcp631/2/3/4/5/9 1.0 electrical characteristics 1.1 absolute maximum ratings ? v dd ?v ss .......................................................................6.5v current at input pins ....................................................2 ma analog inputs (v in + and v in ?) ?? . v ss ? 1.0v to v dd +1.0v all other inputs and outputs .......... v ss ? 0.3v to v dd +0.3v output short-circuit current ................................ continuous current at output and supply pins ..........................150 ma storage temperature ...................................-65c to +150c maximum junction temperature ................................ +150c esd protection on all pins (hbm, mm) ????????????????? 1 kv, 200v ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listi ngs of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. ?? see section 4.1.2 ?input voltage and current limits? . 1.2 specifications dc electrical specifications electrical characteristics: unless otherwise indicated, t a =+25c, v dd = +2.5v to +5.5v, v ss = gnd, v cm =v dd /3, v out ? v dd /2, v l =v dd /2, r l =2k ? to v l and cs =v ss (refer to figure 1-2 ). parameters sym. min. typ. max. units conditions input offset input offset voltage v os -8 1.8 +8 mv input offset voltage drift ? v os / ? t a ?2.0?v/ct a = -40c to +125c power supply rejection ratio psrr 61 76 ? db input current and impedance input bias current i b ?4?pa across temperature i b ? 100 ? pa t a =+85c across temperature i b ? 1500 5000 pa t a = +125c input offset current i os ?2?pa common-mode input impedance z cm ?10 13 ||9 ? ? ||pf differential input impedance z diff ?10 13 ||2 ? ? ||pf common mode common-mode input voltage range v cmr v ss ? 0.3 ? v dd ? 1.3 v note 1 common-mode rejection ratio cmrr 63 78 ? db v dd =2.5v, v cm = -0.3v to 1.2v 66 81 ? db v dd =5.5v, v cm = -0.3v to 4.2v open-loop gain dc open-loop gain (large signal) a ol 88 115 ? db v dd =2.5v, v out = 0.3v to 2.2v 94 124 ? db v dd =5.5v, v out = 0.3v to 5.2v output maximum output voltage swing v ol , v oh v ss +20 ? v dd ? 20 mv v dd =2.5v, g=+2, 0.5v input overdrive v ss +40 ? v dd ? 40 mv v dd =5.5v, g=+2, 0.5v input overdrive output short-circuit current i sc 40 85 130 ma v dd =2.5v ( note 2 ) i sc 35 70 110 ma v dd =5.5v ( note 2 ) power supply supply voltage v dd 2.5 ? 5.5 v quiescent current per amplifier i q 1.2 2.5 3.6 ma no load current note 1: see figure 2-5 for temperature effects. 2: the i sc specifications are for design gui dance only; they are not tested.
mcp631/2/3/4/5/9 ds20002197c-page 4 ? 2009-2014 microchip technology inc. ac electrical specifications electrical characteristics: unless otherwise indicated, t a =+25c, v dd = +2.5v to +5.5v, v ss =gnd, v cm =v dd /2, v out ? v dd /2, v l =v dd /2, r l =2k ? to v l , c l = 50 pf and cs =v ss (refer to figure 1-2 ). parameters sym. min. typ. max. units conditions ac response gain-bandwidth product gbwp ? 24 ? mhz phase margin pm ? 65 ? g = +1 open-loop output impedance r out ?20? ? ac distortion total harmonic distortion plus noise thd + n ? 0.0015 ? % g = +1, v out =2v p-p , f = 1 khz, v dd =5.5v, bw=80khz step response rise time, 10% to 90% t r ?20?nsg=+1, v out = 100 mv p-p slew rate sr ? 10 ? v/s g = +1 noise input noise voltage e ni ?16?v p-p f = 0.1 hz to 10 hz input noise voltage density e ni ?10?nv/ ? hz f = 1 mhz input noise current density i ni 4?fa/ ? hz f = 1 khz digital electrical specifications electrical characteristics: unless otherwise indicated, t a =+25c, v dd = +2.5v to +5.5v, v ss = gnd, v cm =v dd /2, v out ? v dd /2, v l =v dd /2, r l =2k ? to v l , c l = 50 pf and cs =v ss (refer to figures 1-1 and 1-2 ). parameters sym. min. typ. max. units conditions cs low specifications cs logic threshold, low v il v ss ?0.2v dd v cs input current, low i csl ?0.1?nacs =0v cs high specifications cs logic threshold, high v ih 0.8v dd v dd v cs input current, high i csh ?0.7?acs =v dd gnd current i ss -2 -1 ?a cs internal pull-down resistor r pd ?5?m ? amplifier output leakage i o(leak) ?50?nacs =v dd , t a = +125c cs dynamic specifications cs input hysteresis v hyst ? 0.25 ? v cs high to amplifier off time (output goes high z) t off ? 200 ? ns g = +1 v/v, v l =v ss , c s =0.8v dd to v out =0.1(v dd /2) cs low to amplifier on time t on ?210s g=+1v/v, v l =v ss , c s =0.2v dd to v out =0.9(v dd /2)
? 2009-2014 microchip technology inc. ds20002197c-page 5 mcp631/2/3/4/5/9 1.3 timing diagram figure 1-1: timing diagram. 1.4 test circuits the circuit used for most dc and ac tests is shown in figure 1-2 . it independently sets v cm and v out ; see equation 1-1 . the circuit?s common-mode voltage is (v p +v m )/2, not v cm . v ost includes v os plus the effects of temperature, cmrr, psrr and a ol . equation 1-1: temperature specifications electrical characteristics: unless otherwise indicated, all limits are specified for: v dd = +2.5v to +5.5v, v ss = gnd. parameters sym. min. typ. max. units conditions temperature ranges specified temperature range t a -40 ? +125 c operating temperature range t a -40 ? +125 c note 1 storage temperature range t a -65 ? +150 c thermal package resistances thermal resistance, 5l-sot-23 ja ? 201.0 ? c/w thermal resistance, 6l-sot-23 ja ? 190.5 ? c/w thermal resistance, 8l-2x3 tdfn ja ? 52.5 ? c/w thermal resistance, 8l-3x3 dfn ja ? 56.7 ? c/w note 2 thermal resistance, 8l-soic ja ? 149.5 ? c/w thermal resistance, 10l-3x3 dfn ja ? 54.0 ? c/w note 2 thermal resistance, 10l-msop ja ? 202 ? c/w thermal resistance, 14l-soic ja ? 90.8 ? c/w thermal resistance, 14l-tssop ja ? 100 ? c/w thermal resistance, 16l-4x4-qfn ja ? 52.1 ? c/w note 2 note 1: operation must not cause t j to exceed maximum junction te mperature specification (+150c). 2: measured on a standard jc51-7, four-layer pr inted circuit board with ground plane and vias. v out i ss i cs -1 a high z 0.7 a on -2.5 ma -1 a t on t off high z 0.1 na 0.7 a cs v il v ih (typical) (typical) (typical) (typical) (typical) (typical) where: g dm = differential mode gain (v/v) g n = noise gain (v/v) v cm = op amp?s common-mode input voltage (v) v ost = op amp?s total input offset voltage (mv) g dm r f r g ------ - = g n 1g dm + = v cm v p 1 1 g n ------- ? ?? ?? v ref 1 g n ------- ?? ?? + = v ost v in- v in+ ? = v out v ref v p v m ? ?? g dm v ost g n ++ =
mcp631/2/3/4/5/9 ds20002197c-page 6 ? 2009-2014 microchip technology inc. figure 1-2: ac and dc test circuit for most specifications. v dd r g r f v out v m c b2 c l r l v l c b1 10 k ? 10 k ? r g r f v ref =v dd /2 v p 10 k ? 10 k ? 50 pf 2k ? 2.2 f 100 nf v in - v in + c f c f 6.8 pf mcp63x 6.8 pf
? 2009-2014 microchip technology inc. ds20002197c-page 7 mcp631/2/3/4/5/9 2.0 typical performance curves note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k ?? to v l , c l = 50 pf and cs =v ss . 2.1 dc signal inputs figure 2-1: input offset voltage. figure 2-2: input offset voltage drift. figure 2-3: input offset voltage vs. power supply voltage with v cm =0v. figure 2-4: input offset voltage vs. output voltage. figure 2-5: low-input common-mode voltage headroom vs. ambient temperature. figure 2-6: high-input common-mode voltage headroom vs. ambient temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 0% 2% 4% 6% 8% 10% 12% 14% -6-5-4-3-2-10123456 input offset voltage (mv) percentage of occurrences 396 samples t a = +25c v dd = 2.5v and 5.5v 0% 2% 4% 6% 8% 10% 12% 14% 16% -8-7-6-5-4-3-2-1012345678 input offset voltage drift (v/c) percentage of occurrences 398 samples v dd = 2.5v and 5.5v t a = -40c to +125c -4.0 -3.8 -3.6 -3.4 -3.2 -3.0 -2.8 -2.6 -2.4 -2.2 -2.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) input offset voltage (mv) +125c +85c +25c -40c representative part v cm = v ss -3.0 -2.8 -2.6 -2.4 -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 output voltage (v) input offset voltage (mv) v dd = 2.5v v dd = 5.5v representative part -0.5 -0.4 -0.3 -0.2 -0.1 0.0 -50 -25 0 25 50 75 100 125 ambient temperature (c) low input common mode headroom (v) 1 lot low (v cmr_l ? v ss ) v dd = 2.5v and 5.5v 0.9 1.0 1.1 1.2 1.3 -50 -25 0 25 50 75 100 125 ambient temperature (c) high input common mode headroom (v) v dd = 2.5v v dd = 5.5v 1 lot high (v dd ? v cmr_h )
mcp631/2/3/4/5/9 ds20002197c-page 8 ? 2009-2014 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k ?? to v l , c l = 50 pf and cs =v ss . figure 2-7: input offset voltage vs. common-mode voltage with v dd =2.5v. figure 2-8: input offset voltage vs. common-mode voltage with v dd =5.5v. figure 2-9: cmrr and psrr vs. ambient temperature. figure 2-10: dc open-loop gain vs. ambient temperature. figure 2-11: dc open-loop gain vs. load resistance. figure 2-12: input bias and offset currents vs. ambient temperature with v dd =5.5v. -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 input common mode voltage (v) input offset voltage (mv) v dd = 2.5v representative part +125c +85c +25c -40c -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input common mode voltage (v) input offset voltage (mv) v dd = 5.5v representative part +125c +85c +25c -40c 60 65 70 75 80 85 90 95 100 105 110 -50 -25 0 25 50 75 100 125 ambient temperature (c) cmrr, psrr (db) psrr cmrr, v dd = 2.5v cmrr, v dd = 5.5v 100 105 110 115 120 125 130 -50 -25 0 25 50 75 100 125 ambient temperature (c) dc open-loop gain (db) v dd = 5.5v v dd = 2.5v 95 100 105 110 115 120 125 130 1.e+02 1.e+03 1.e+04 1.e+05 load resistance ( ? ) dc open-loop gain (db) v dd = 5.5v v dd = 2.5v 100 1k 10k 100k 1.e-12 1.e-11 1.e-10 1.e-09 1.e-08 25 45 65 85 105 125 ambient temperature (c) input bias, offset currents (pa) v dd = 5.5v v cm = v cmr_h | i os | i b 1p 10p 100p 1n 10n
? 2009-2014 microchip technology inc. ds20002197c-page 9 mcp631/2/3/4/5/9 note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k ?? to v l , c l = 50 pf and cs =v ss . figure 2-13: input bias current vs. input voltage (below v ss ). figure 2-14: input bias and offset currents vs. common-mode input voltage with t a = +85c. figure 2-15: input bias and offset currents vs. common-mode input voltage with t a = +125c. 1.e-12 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 1.e-05 1.e-04 1.e-03 -1.0 -0.9 -0.8 -0.7 -0.6 -0 .5 -0.4 -0.3 -0.2 -0.1 0.0 input voltage (v) input current magnitude (a) +125c +85c +25c -40c 1m 100 10 1 100n 10n 1n 100p 10p 1p -200 -150 -100 -50 0 50 100 150 200 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) input bias, offset currents (pa) i b representative part t a = +85c v dd = 5.5v i os -1500 -1000 -500 0 500 1000 1500 2000 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) input bias, offset currents (pa) i b representative part t a = +125c v dd = 5.5v i os
mcp631/2/3/4/5/9 ds20002197c-page 10 ? 2009-2014 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k ?? to v l , c l = 50 pf and cs =v ss . 2.2 other dc voltages and currents figure 2-16: output voltage headroom vs. output current. figure 2-17: output voltage headroom vs. ambient temperature. figure 2-18: output short-circuit current vs. power supply voltage. figure 2-19: supply current vs. power supply voltage. figure 2-20: supply current vs. common-mode input voltage. 1 10 100 1000 0.1 1 10 100 output current magnitude (ma) output voltage headroom (mv) v dd = 2.5v v dd = 5.5v v dd ? v oh v ol ? v ss 0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 ambient temperature (c) output headroom (mv) v dd = 5.5v v ol ? v ss v dd = 2.5v v dd ? v oh r l = 2 k ? -100 -80 -60 -40 -20 0 20 40 60 80 100 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) output short circuit current (ma) +125c +85c +25c -40c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) supply current (ma/amplifier) +125c +85c +25c -40c 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) supply current (ma/amplifier) v dd = 2.5v v dd = 5.5v
? 2009-2014 microchip technology inc. ds20002197c-page 11 mcp631/2/3/4/5/9 note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k ?? to v l , c l = 50 pf and cs =v ss . 2.3 frequency response figure 2-21: cmrr and psrr vs. frequency. figure 2-22: open-loop gain vs. frequency. figure 2-23: gain-bandwidth product and phase margin vs. ambient temperature. figure 2-24: gain-bandwidth product and phase margin vs. common-mode input voltage. figure 2-25: gain-bandwidth product and phase margin vs. output voltage. figure 2-26: closed-loop output impedance vs. frequency. 10 20 30 40 50 60 70 80 90 100 1.e+2 1.e+3 1.e+4 1.e+5 1.e+6 1.e+7 frequency (hz) cmrr, psrr (db) 100 1m 10k 10m 100k 1k cmrr psrr+ psrr- -20 0 20 40 60 80 100 120 140 1.e+0 1.e+1 1.e+2 1.e+3 1.e+4 1.e+5 1.e+6 1.e+7 1.e+8 frequency (hz) open-loop gain (db) -240 -210 -180 -150 -120 -90 -60 -30 0 open-loop phase () | a ol | ? a ol 100 10k 1m 100m 1 1k 100k 10m 10 20 22 24 26 28 30 32 34 36 -50 -25 0 25 50 75 100 125 ambient temperature (c) gain bandwidth product (mhz) 40 45 50 55 60 65 70 75 80 phase margin () pm gbwp v dd = 5.5v v dd = 2.5v 20 22 24 26 28 30 32 34 36 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) gain bandwidth product (mhz) 40 45 50 55 60 65 70 75 80 phase margin () pm gbwp v dd = 5.5v v dd = 2.5v 20 22 24 26 28 30 32 34 36 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 output voltage (v) gain bandwidth product (mhz) 40 45 50 55 60 65 70 75 80 phase margin () pm gbwp v dd = 5.5v v dd = 2.5v 0.1 1 10 100 1.0e+04 1.0e+05 1.0e+06 1.0e+07 1.0e+08 frequency (hz) 10k 1m 10m 100m closed-loop output impedance ( ? ) 100k g = 101 v/v g = 11 v/v g = 1 v/v
mcp631/2/3/4/5/9 ds20002197c-page 12 ? 2009-2014 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k ?? to v l , c l = 50 pf and cs =v ss . figure 2-27: gain peaking vs. normalized capacitive load. figure 2-28: channel-to-channel separation vs. frequency. 0 1 2 3 4 5 6 7 8 9 10 1.0e-11 1.0e-10 1.0e-09 normalized capacitive load; c l /g n (f) gain peaking (db) 10p 100p 1n g n = 1 v/v g n = 2 v/v g n ? 50 60 70 80 90 100 110 120 130 140 150 1.e+03 1.e+04 1.e+05 1.e+06 1.e+07 frequency (hz) channel-to-channel separation; rti (db) 1k 10k 100k v cm = v dd /2 g = +1 v/v r s = 10 k ? r s = 100 k ? 1m 10m r s = 0 ? r s = 100 ? r s = 1 k ?
? 2009-2014 microchip technology inc. ds20002197c-page 13 mcp631/2/3/4/5/9 note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k ?? to v l , c l = 50 pf and cs =v ss . 2.4 noise and distortion figure 2-29: input noise voltage density vs. frequency. figure 2-30: input noise voltage density vs. input common-mode voltage with f=100hz. figure 2-31: input noise voltage density vs. input common-mode voltage with f = 1 mhz. figure 2-32: input noise vs. time with 0.1 hz filter. figure 2-33: thd+n vs. frequency. 1.e+0 1.e+1 1.e+2 1.e+3 1.e+4 1.e-1 1.e+0 1.e+1 1.e+2 1.e+3 1.e+4 1.e+5 1.e+6 1.e+7 frequency (hz) 0.1 100 10k 1m input noise voltage density (v/ ? hz) 1 1k 100k 10m 10 1n 100n 1 10 10n 0 20 40 60 80 100 120 140 160 180 200 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 common mode input voltage (v) v dd = 5.5v v dd = 2.5v input noise voltage density (nv/ ? hz) f = 100 hz 0 2 4 6 8 10 12 14 16 18 20 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 common mode input voltage (v) v dd = 5.5v v dd = 2.5 v input noise voltage density (nv/ ? hz) f = 1 mhz -20 -15 -10 -5 0 5 10 15 20 0 5 10 15 20 25 30 35 40 45 50 55 60 65 time (min) input noise; e ni (t) (v) representative part analog npbw = 0.1 hz sample rate = 2 sps v os = -3150 v 0.0001 0.001 0.01 0.1 1 1.e+2 1.e+3 1.e+4 1.e+5 frequency (hz) thd + noise (%) v dd = 5.0v v out = 2 v p-p 100 1k 10k 100k bw = 22 hz to 80 khz bw = 22 hz to > 500 khz g = 1 v/v g = 11 v/v
mcp631/2/3/4/5/9 ds20002197c-page 14 ? 2009-2014 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k ?? to v l , c l = 50 pf and cs =v ss . 2.5 time response figure 2-34: non-inverting small signal step response. figure 2-35: non-inverting large signal step response. figure 2-36: inverting small signal step response. figure 2-37: inverting large signal step response. figure 2-38: the mcp631/2/3/4/5/9 family shows no input phase reversal with overdrive. figure 2-39: slew rate vs. ambient temperature. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 time (s) output voltage (10 mv/div) v dd = 5.5v g = 1 v in v out 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.00.20.40.60.81.01.21.41.61.82.0 time (s) output voltage (v) v dd = 5.5v g = 1 v in v out 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 time (s) output voltage (10 mv/div) v dd = 5.5v g = -1 r f = 1 k ? v in v out 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 time (s) output voltage (v) v dd = 5.5v g = -1 r f = 1 k ? v in v out -1 0 1 2 3 4 5 6 7 012345678910 time (ms) input, output voltages (v) v dd = 5.5v g = 2 v out v in 0 2 4 6 8 10 12 14 16 18 20 22 24 -50 -25 0 25 50 75 100 125 ambient temperature (c) slew rate (v/s) falling edge rising edge v dd = 2.5v v dd = 5.5v
? 2009-2014 microchip technology inc. ds20002197c-page 15 mcp631/2/3/4/5/9 note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k ?? to v l , c l = 50 pf and cs =v ss . figure 2-40: maximum output voltage swing vs. frequency. 0.1 1 10 1.e+05 1.e+06 1.e+07 1.e+08 frequency (hz) maximum output voltage swing (v p-p ) v dd = 5.5v v dd = 2.5v 100k 1m 10m 100m
mcp631/2/3/4/5/9 ds20002197c-page 16 ? 2009-2014 microchip technology inc. note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k ?? to v l , c l = 50 pf and cs =v ss . 2.6 chip select response figure 2-41: cs current vs. power supply voltage. figure 2-42: cs and output voltages vs. time with v dd =2.5v. figure 2-43: cs and output voltages vs. time with v dd =5.5v. figure 2-44: cs hysteresis vs. ambient temperature. figure 2-45: cs turn-on time vs. ambient temperature. figure 2-46: cs pull-down resistor (r pd ) vs. ambient temperature. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 power supply voltage (v) cs current (a) cs = v dd -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 2 4 6 8 101214161820 time (s) cs, v out (v) v dd = 2.5v g = 1 v l = 0v on cs v out off off -1 0 1 2 3 4 5 6 0 2 4 6 8 101214161820 time (s) cs, v out (v) v dd = 5.5v g = 1 v l = 0v on cs v out off off 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 -50 -25 0 25 50 75 100 125 ambient temperature (c) cs hysteresis (v) v dd = 2.5v v dd = 5.5v 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 ambient temperature (c) cs turn on time (s) v dd = 2.5v v dd = 5.5v 0 1 2 3 4 5 6 7 8 -50 -25 0 25 50 75 100 125 ambient temperature (c) cs pull-down resistor (m ? ) representative part
? 2009-2014 microchip technology inc. ds20002197c-page 17 mcp631/2/3/4/5/9 note: unless otherwise indicated, t a =+25c, v dd = +2.5v to 5.5v, v ss = gnd, v cm =v dd /3, v out =v dd /2, v l =v dd /2, r l =2k ?? to v l , c l = 50 pf and cs =v ss . figure 2-47: quiescent current in shutdown vs. power supply voltage. figure 2-48: output leakage current vs. output voltage. -2.2 -2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 power supply voltage (v) negative power supply current; i ss (a) cs = v dd -40c +25c +85c +125c 1.e-11 1.e-10 1.e-09 1.e-08 1.e-07 1.e-06 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 output voltage (v) output leakage current (a) +25c +125c +85c cs = v dd = 5.5v 1 100n 10n 1n 100p 10p
mcp631/2/3/4/5/9 ds20002197c-page 18 ? 2009-2014 microchip technology inc. 3.0 pin descriptions descriptions of the pins are listed in table 3-1 . table 3-1: pin function table mcp631 mcp632 mcp633 mcp634 mcp635 mcp639 symbol description soic sot -23 2x3 tdfn soic 3x3 dfn soic sot- 23 soic tssop msop 3x3 dfn qfn 242 222 4 2 2 2 21 v in -, v ina - inverting input (op amp a) 333 333 3 3 3 3 32v in +, v ina + non-inverting input (op amp a) 757 887 6 4 4 10103 v dd positive power supply ?? ? 5 5 ? ? 5 5 7 7 4 v inb + non-inverting input (op amp b) ?? ? 6 6 ? ? 6 6 8 8 5 v inb - inverting input (op amp b) ?? ? 7 7 ? ? 7 7 9 9 6 v outb output (op amp b) ?? ? ??? ? ? ? ? ? 7 cs bc chip select digital input (op amp b and c) ?? ? ??? ? 8 8 ? ? 8 v outc output (op amp c) ?? ? ??? ? 9 9 ? ? 9 v inc - inverting input (op amp c) ?? ? ??? ? 10 10 ? ?10v inc + non-inverting input (op amp c) 424 444 211 11 4 411v ss negative power supply ?? ? ??? ? 12 12 ? ?12v ind + non-inverting input (op amp d) ?? ? ??? ? 13 13 ? ?13 v ind - inverting input (op amp d) ?? ? ??? ? 14 14 ? ?14v outd output (op amp d) ?? ? ??? ? ? ? ? ?15 cs ad chip select digital input (op amp a and d) 616 116 1 1 1 1 116v out , v outa output (op amp a) ? ? 9 ? 9 ? ? ? ? ? 11 17 ep exposed thermal pad (ep); must be connected to v ss ?? ? ?? 8 5 ? ? 5 5?cs , cs a chip select digital input (op amp a) ?? ? ??? ? ? ? 6 6? cs b chip select digital input (op amp b) 1,5, 8 ?1, 5, 8 ? ? 1, 5 ? ? ? ? ? ? nc no internal connection
? 2009-2014 microchip technology inc. ds20002197c-page 19 mcp631/2/3/4/5/9 3.1 analog outputs the analog output pins (v out ) are low-impedance voltage sources. 3.2 analog inputs the non-inverting and inverting inputs (v in +, v in -, ?) are high-impedance cmos inputs with low bias currents. 3.3 power supply pins the positive power supply (v dd ) is 2.5v to 5.5v higher than the negative power supply (v ss ). for normal operation, the other pins are between v ss and v dd . typically, these parts are used in a single (positive) supply configuration. in that case, v ss is connected to ground and v dd is connected to the supply. v dd will need bypass capacitors. 3.4 chip select digital input (cs ) this input (cs ) is a cmos, schmitt-triggered input that places the part into a low-power mode of operation. 3.5 exposed thermal pad (ep) there is an internal connection between the exposed thermal pad (ep) and the v ss pin; they must be connected to the same potential on the printed circuit board (pcb). this pad can be connected to a pcb ground plane to provide a larger heat sink. this improves the package thermal resistance ( ? ja ).
mcp631/2/3/4/5/9 ds20002197c-page 20 ? 2009-2014 microchip technology inc. 4.0 applications the mcp631/2/3/4/5/9 family is manufactured using the microchip state-of-the-art cmos process. it is designed for low-cost, low-power and high-speed applications. its low supply voltage, low quiescent current and wide bandwidth make the mcp631/2/3/4/5/9 ideal for battery-powered applications. 4.1 input 4.1.1 phase reversal the input devices are designed to exhibit no phase inversion when the input pins exceed the supply voltages. figure 2-38 shows an input voltage exceeding both supplies with no phase inversion. 4.1.2 input voltage and current limits the electrostatic discharge (esd) protection on the inputs can be depicted as shown in figure 4-1 . this structure was chosen to protect the input transistors and to minimize input bias current (i b ). the input esd diodes clamp the inputs when they try to go more than one diode drop below v ss . they also clamp any voltages that go too far above v dd ; their breakdown voltage is high enough to allow normal operation and low enough to bypass quick esd events within the specified limits. figure 4-1: simplified analog input esd structures. in order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at the input pins (see section 1.1 ?absolute maximum ratings ?? ). figure 4-2 shows the recommended approach to protecting these inputs. the internal esd diodes prevent the input pins (v in + and v in -) from going too far below ground, while the resistors r 1 and r 2 limit the possible current drawn out of the input pins. diodes d 1 and d 2 prevent the input pins (v in + and v in -) from going too far above v dd and dump any currents onto v dd . when implemented as shown, resistors r 1 and r 2 also limit the current through d 1 and d 2 . figure 4-2: protecting the analog inputs. it is also possible to connect the diodes to the left of the resistors r 1 and r 2 . if so, the currents through the diodes d 1 and d 2 need to be limited by some other mechanism. the resistors then serve as in-rush current limiters; the dc current into the input pins (v in + and v in -) should be very small. a significant amount of current can flow out of the inputs (through the esd diodes) when the common-mode voltage (v cm ) is below ground (v ss ); see figure 2-13 . applications that are high-impedance may need to limit the usable voltage range. 4.1.3 normal operation the input stage of the mcp631/2/3/4/5/9 op amps uses a differential pmos input stage. it operates at low common-mode input voltages (v cm ), with v cm between v ss ? 0.3v and v dd ? 1.3v. to ensure proper operation, the input offset voltage (v os ) is measured at both v cm =v ss ? 0.3v and v cm =v dd ?1.3v. see figures 2-5 and 2-6 for temperature effects. when operating at very low non-inverting gains, the output voltage is limited at the top by the v cm range (< v dd ? 1.3v); see figure 4-3 . figure 4-3: unity-gain voltage limitations for linear operation. bond pad bond pad bond pad v dd v in + v ss input stage bond pad v in - v 1 r 1 v dd d 1 v out v 2 r 2 d 2 mcp63x r 1 v ss minimum expected v 1 ?? ? 2ma ------------------------------------------------------------------------ ? r 2 v ss minimum expected v 2 ?? ? 2ma ------------------------------------------------------------------------ ? v in v dd v out mcp63x + - v ss v in ? v out v dd 1.3v ? ?
? 2009-2014 microchip technology inc. ds20002197c-page 21 mcp631/2/3/4/5/9 4.2 rail-to-rail output 4.2.1 maximum output voltage the maximum output voltage (see figures 2-16 and 2-17 ) describes the output range for a given load. for instance, the output voltage swings to within 50 mv of the negative rail with a 1 k ? load tied to v dd /2. 4.2.2 output current figure 4-4 shows the possible combinations of output voltage (v out ) and output current (i out ), when v dd =5.5v. i out is positive when it flows out of the op amp into the external circuit. figure 4-4: output current. 4.2.3 power dissipation since the output short-circuit current (i sc ) is specified at 70 ma (typical), these op amps are capable of both delivering and dissipating significant power. figure 4-5: diagram for power calculations. figure 4-5 shows the power calculations used for a single op amp: ?r ser is 0 ? in most applications and can be used to limit i out . ?v out is the op amp?s output voltage. ?v l is the voltage at the load. ?v lg is the load?s ground point. ?v ss is usually ground (0v). the input currents are assumed to be negligible. the currents shown in figure 4-5 can be approximated using equation 4-1 : equation 4-1: the instantaneous op amp power (p oa (t)), r ser power (p rser (t)) and load power (p l (t)) are: equation 4-2: the maximum op amp power, for resistive loads, occurs when v out is halfway between v dd and v lg or halfway between v ss and v lg . equation 4-3: the maximum ambient to junction temperature rise ( ? t ja ) and junction temperature (t j ) can be calculated using p oamax , the ambient temperature (t a ), the package thermal resistance ( ? ja , found in the temperature specifications table) and the number of op amps in the package (assuming equal power dissipations), as shown in equation 4-4 : equation 4-4: -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -120 -100 -80 -60 -40 -20 0 20 40 60 80 100 120 i out (ma) v out (v) r l = 10 ? r l = 100 ? r l = 1 k ? v oh limited v ol limited -i sc limited +i sc limited (v dd = 5.5v) v dd v l r l v lg i dd i ss i l i out r ser v out v ss mcp63x + - where: i q = quiescent supply current i out i l v out v lg ? r ser r l + ----------------------------- - == i dd i q max 0, i out ?? + ? i ss i ? q min 0, i out ?? + ? p oa (t) = i dd (v dd ? v out ) + i ss (v ss ? v out ) p rser (t) = i out 2 r ser p l (t) = i l 2 r l p oamax max 2 v dd v lg ? v lg v ss ? ? ?? 4r ser r l + ?? ------------------------------------------------------------------------- ? where: n = number of op amps in the package (1, 2) t ja ? p oa t ?? ? ja np oamax ? ja ? = t j t a t ja ? + =
mcp631/2/3/4/5/9 ds20002197c-page 22 ? 2009-2014 microchip technology inc. the power derating across temperature for an op amp in a particular package can be easily calculated (assuming equal power dissipations): equation 4-5: several techniques are available to reduce ? t ja for a given p oamax : ? lower ? ja - use another package - pcb layout (ground plane, etc.) - heat sinks and air flow ? reduce p oamax - increase r l - limit i out (using r ser ) - decrease v dd 4.3 improving stability 4.3.1 capacitive loads driving large capacitive loads can cause stability problems for voltage feedback op amps. as the load capacitance increases, the phase margin (stability) of the feedback loop decreases and the closed-loop bandwidth is reduced. this produces gain peaking in the frequency response, with overshoot and ringing in the step response. a unity-gain buffer (g = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. when driving large capacitive loads with these op amps (e.g., > 20 pf when g = +1), a small series resistor at the output (r iso in figure 4-6 ) improves the phase margin of the feedback loop by making the output load resistive at higher frequencies. the bandwidth will be generally lower than the bandwidth with no capacitive load. figure 4-6: output resistor, r iso , stabilizes large capacitive loads. figure 4-7 gives recommended r iso values for different capacitive loads and gains. the x-axis is the normalized load capacitance (c l /g n ), where g n is the circuit?s noise gain. for non-inverting gains, g n and the signal gain are equal. for inverting gains, g n is 1 + |signal gain| (e.g., -1 v/v gives g n =+2v/v). figure 4-7: recommended r iso values for capacitive loads. after selecting r iso , double-check the resulting frequency response peaking and step response overshoot. modify the value of r iso until the response is reasonable. bench evaluation and simulations with the mcp631/2/3/4/5/9 spice macro model are helpful. 4.3.2 gain peaking figure 4-8 shows an op amp circuit that represents non-inverting amplifiers (v m is a dc voltage and v p is the input) or inverting amplifiers (v p is a dc voltage and v m is the input). the capacitances c n and c g represent the total capacitance at the input pins; they include the op amp?s common-mode input capacitance (c cm ), board parasitic capacitance and any capacitor placed in parallel. figure 4-8: amplifier with parasitic capacitance. c g acts in parallel with r g (except for a gain of +1 v/v), which causes an increase in gain at high frequencies. c g also reduces the phase margin of the feedback loop, which becomes less stable. this effect can be reduced by either reducing c g or r f . c n and r n form a low-pass filter that affects the signal at v p . this filter has a single real pole at 1/(2 ? r n c n ). where: t jmax = absolute maximum junction temperature p oamax t jmax t a ? n ? ja -------------------------- ? mcp63x - + 10 100 1,000 1.e-12 1.e-11 1.e-10 1.e-09 1.e-08 normalized capacitance; c l /g n (f) recommended r iso ( ? ) g n = +1 g n ? +2 10p 100p 1n 10n v p r f v out r n c n v m r g c g mcp63x + -
? 2009-2014 microchip technology inc. ds20002197c-page 23 mcp631/2/3/4/5/9 the largest value of r f that should be used depends on the noise gain (see g n in section 4.3.1 ?capacitive loads? ), c g and the open-loop gain?s phase shift. figure 4-9 shows the maximum recommended r f for several c g values. some applications may modify these values to reduce either output loading or gain peaking (step response overshoot). figure 4-9: maximum recommended r f vs. gain. figures 2-34 and 2-35 show the small signal and large signal step responses at g = +1 v/v. the unity-gain buffer usually has r f =0 ? and r g open. figures 2-36 and 2-37 show the small signal and large signal step responses at g = -1 v/v. since the noise gain is 2 v/v and c g ? 10 pf, the resistors were chosen to be r f =r g =1k ? and r n = 500 ? . it is also possible to add a capacitor (c f ) in parallel with r f to compensate for the destabilizing effect of c g . this makes it possible to use larger values of r f . the conditions for stability are summarized in equation 4-6 . equation 4-6: 4.4 mcp633, mcp635 and mcp639 chip select the mcp633 is a single amplifier with chip select (cs ). when cs is pulled high, the supply current drops to 1 a (typical) and flows through the cs pin to v ss . when this happens, the amplifier output is put into a high-impedance state. by pulling cs low, the amplifier is enabled. the cs pin has an internal 5 m ? (typical) pull-down resistor connected to v ss , so it will go low if the cs pin is left floating. figures 1-1 , 2-42 and 2-43 show the output voltage and supply current response to a cs pulse. the mcp635 is a dual amplifier with two cs pins; cs a controls op amp a and cs b controls op amp b. these op amps are controlled independently, with an enabled quiescent current (i q ) of 2.5 ma/amplifier (typical) and a disabled i q of 1 a/amplifier (typical). the i q seen at the supply pins is the sum of the two op amps? i q ; the typical value for the i q of the mcp635 will be 2 a, 2.5 ma or 5 ma when there are 0, 1 or 2 amplifiers enabled, respectively. the mcp639 is a quad amplifier with two cs pins; cs b controls op amp b and cs d controls op amp d. 4.5 power supply with this family of operational amplifiers, the power supply pin (v dd for single supply) should have a local bypass capacitor (i.e., 0.01 f to 0.1 f) within 2 mm for good high-frequency performance. surface mount, multilayer ceramic capacitors, or their equivalent, should be used. these op amps require a bulk capacitor (i.e., 2.2 f or larger) within 50 mm to provide large, slow currents. tantalum capacitors, or their equivalent, may be a good choice. this bulk capacitor can be shared with other nearby analog parts as long as crosstalk through the supplies does not prove to be a problem. 1.e+02 1.e+03 1.e+04 1.e+05 1 10 100 noise gain; g n (v/v) maximum recommended r f ( ? ) g n > +1 v/v 100 10k 100k 1k c g = 10 pf c g = 32 pf c g = 100 pf c g = 320 pf c g = 1 nf we need: given: g n1 1 r f r g ------ - + = g n2 1 c g c f ------- + = f f 1 2 ? r f c f -------------------- - = f z f f g n1 g n2 --------- - ?? ?? = f f f gbwp 2g n2 --------------- , ? g n1 g n2 ? f f f gbwp 4g n1 --------------- , ? g n1 g n2 ?
mcp631/2/3/4/5/9 ds20002197c-page 24 ? 2009-2014 microchip technology inc. 4.6 high-speed pcb layout these op amps are fast enough that a little extra care in the printed circuit board (pcb) layout can make a significant difference in performance. good pcb layout techniques will help achieve the performance shown in the specifications and typical performance curves; it will also help minimize electromagnetic compatibility (emc) issues. use a solid ground plane. connect the bypass local capacitor(s) to this plane with minimal length traces. this cuts down inductive and capacitive crosstalk. separate digital from analog, low-speed from high-speed, and low-power from high-power. this will reduce interference. keep sensitive traces short and straight. separate them from interfering components and traces. this is especially important for high-frequency (low rise time) signals. sometimes, it helps to place guard traces next to victim traces. they should be on both sides of the victim trace and as close as possible. connect guard traces to ground plane at both ends and in the middle for long traces. use coax cables, or low-inductance wiring, to route signal and power to and from the pcb. mutual and self-inductance of power wires is often a cause of crosstalk and unusual behavior. 4.7 typical applications 4.7.1 power driver with high gain figure 4-10 shows a power driver with high gain (1 + r 2 /r 1 ). the short-circuit current of the mcp631/2/3/4/5/9 op amps makes it possible to drive significant loads. the calibrated input offset voltage supports accurate response at high gains. r 3 should be small and equal to r 1 ||r 2 in order to minimize the bias current induced offset. figure 4-10: power driver. 4.7.2 optical detector amplifier figure 4-11 shows a transimpedance amplifier, using the mcp63x op amp, in a photo detector circuit. the photo detector is a capacitive current source. r f provides enough gain to produce 10 mv at v out . c f stabilizes the gain and limits the transimpedance bandwidth to about 1.1 mhz. the parasitic capacitance of r f (e.g., 0.2 pf for a 0805 smd) acts in parallel with c f . figure 4-11: transimpedance amplifier for an optical detector. 4.7.3 h-bridge driver figure 4-12 shows the mcp632 dual op amp used as a h-bridge driver. the load could be a speaker or a dc motor. figure 4-12: h-bridge driver. this circuit automatically makes the noise gains (g n ) equal when the gains are set properly, so that the frequency responses match well (in magnitude and in phase). equation 4-7 shows how to calculate r gt and r gb so that both op amps have the same dc gains; g dm needs to be selected first. r 1 r 2 v in v dd /2 v out r 3 r l mcp63x - + photo detector c d c f r f v dd /2 30 pf 100 k ? 1.5 pf i d 100 na v out mcp632 - + r f r f v in v ot r f r gb v ob v dd /2 r gt r l ? mcp633 ? mcp633 + - - +
? 2009-2014 microchip technology inc. ds20002197c-page 25 mcp631/2/3/4/5/9 equation 4-7: equation 4-8 gives the resulting common-mode and differential mode output voltages. equation 4-8: g dm v ot v ob ? v in v dd 2 ---------- - ? -------------------------- 1 v / v ? ? r gt r f g dm 2 ----------- -1 ? -------------------- - = r gb r f g dm 2 ----------- - ----------- - = v ot v + ob 2 --------------------------- v dd 2 ---------- - = v ot v ? ob g dm v in v dd 2 ---------- - ? ?? ?? =
mcp631/2/3/4/5/9 ds20002197c-page 26 ? 2009-2014 microchip technology inc. 5.0 design aids microchip provides the basic design aids needed for the mcp631/2/3/4/5/9 family of op amps. 5.1 spice macro model the latest spice macro model for the mcp631/2/3/4/5/9 op amps is available on the microchip web site at www.microchip.com . this model is intended to be an initial design tool that works well in the linear region of operation over the temperature range of the op amp. see the model file for information on its capabilities. bench testing is a very important part of any design and cannot be replaced with simulations. also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 filterlab ? software microchip?s filterlab ? software is an innovative software tool that simplifies analog active filter (using op amps) design. available at no cost from the microchip web site at www.microchip.com/filterlab , the filterlab design tool provides full schematic diagrams of the filter circuit with component values. it also outputs the filter circuit in spice format, which can be used with the macro model to simulate actual filter performance. 5.3 microchip advanced part selector (maps) maps is a software tool that helps efficiently identify microchip devices that fit a particular design requirement. available at no cost from the microchip web site at www.microchip.com/maps , the maps is an overall selection tool for microchip?s product portfolio that includes analog, memory, mcus and dscs. using this tool, a filter can be defined to sort features for a parametric search of devices and export side-by-side technical comparison reports. helpful links are also provided for data sheets, purchase and sampling of microchip parts. 5.4 analog demonstration and evaluation boards microchip offers a broad spectrum of analog demonstration and evaluation boards that are designed to help customers achieve faster time to market. for a complete listing of these boards and their corresponding user?s guides and technical information, visit the microchip web site at www.microchip.com/analog tools . some boards that are especially useful are: ? mcp6xxx amplifier evaluation board 1 , part number: mcp6xxxev-amp1 ? mcp6xxx amplifier evaluation board 2 , part number: mcp6xxxev-amp2 ? mcp6xxx amplifier evaluation board 3 , part number: mcp6xxxev-amp3 ? mcp6xxx amplifier evaluation board 4 , part number: mcp6xxxev-amp4 ? active filter demo board kit , part number: mcp6xxxdm-fltr ? 8-pin soic/msop/tssop/dip evaluation board , part number: soic8ev 5.5 application notes the following microchip analog design note and application notes are available on the microchip web site at www.microchip.com/appnotes and are recommended as supplemental reference resources. ? adn003: ?select the right operational amplifier for your filtering circuits? , ds21821 ? an722: ?operational amplifier topologies and dc specifications? , ds00722 ? an723: ?operational amplifier ac specifications and applications? , ds00723 ? an884: ?driving capacitive loads with op amps? , ds00884 ? an990: ?analog sensor conditioning circuits ? an overview? , ds00990 ? an1228: ?op amp precision design: random noise? , ds01228 some of these application notes, and others, are listed in the ?signal chain design guide? , ds21825.
? 2009-2014 microchip technology inc. ds20002197c-page 27 mcp631/2/3/4/5/9 6.0 packaging information 6.1 package marking information xxnn xxnn legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 5-lead sot-23 (mcp631) example yv25 6-lead sot-23 (mcp633) example jc25 8-lead tdfn (2x3x0.75 mm) (mcp631) example abk 425 25 8-lead dfn (3x3x0.9 mm) (mcp632) example dabm 1425 256 device code mcp632t-e/mf dabm note 1: applies to 8-lead 3x3 dfn
mcp631/2/3/4/5/9 ds20002197c-page 28 ? 2009-2014 microchip technology inc. nnn (mcp631, mcp632) example mcp631e sn^^1425 256 3 e 10-lead dfn (3x3x0.9 mm) (mcp635) example device code mcp635t-e/mf bafb note 1: applies to 10-lead 3x3 dfn bafb 1425 256 10-lead msop (3x3 mm) (mcp635) example 665 eun 425256 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
? 2009-2014 microchip technology inc. ds20002197c-page 29 mcp631/2/3/4/5/9 14-lead soic (3.90 mm) (mcp634) example mcp634 e/sl^^ 1425256 3 e 14-lead tssop (4.4 mm) (mcp634) example yyww nnn xxxxxxxx 634 e/st 1425 256 16-lead qfn (4x4x0.9 mm) (mcp639) example pin 1 pin 1 639 e/ml^^ 1425256 3 e legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
mcp631/2/3/4/5/9 ds20002197c-page 30 ? 2009-2014 microchip technology inc. n b e e1 d 1 2 3 e e1 a a1 a2 c l l1
? 2009-2014 microchip technology inc. ds20002197c-page 31 mcp631/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp631/2/3/4/5/9 ds20002197c-page 32 ? 2009-2014 microchip technology inc. 6-lead plastic small outline transistor (chy) [sot-23] notes: 1. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.127 mm per side. 2. dimensioning and tolerancing per asme y14.5m. bsc: basic dimension. theoretically exact value shown without tolerances. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging units millimeters dimension limits min nom max number of pins n 6 pitch e 0.95 bsc outside lead pitch e1 1.90 bsc overall height a 0.90 C 1.45 molded package thickness a2 0.89 C 1.30 standoff a1 0.00 C 0.15 overall width e 2.20 C 3.20 molded package width e1 1.30 C 1.80 overall length d 2.70 C 3.10 foot length l 0.10 C 0.60 footprint l1 0.35 C 0.80 foot angle i 0 C 30 lead thickness c 0.08 C 0.26 lead width b 0.20 C 0.51 b e 4 n e1 pin1idby laser mark d 1 2 3 e e1 a a1 a2 c l l1 microchip technology drawing c04-028b
? 2009-2014 microchip technology inc. ds20002197c-page 33 mcp631/2/3/4/5/9 6-lead plastic small outline transistor (chy) [sot-23] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp631/2/3/4/5/9 ds20002197c-page 34 ? 2009-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2014 microchip technology inc. ds20002197c-page 35 mcp631/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp631/2/3/4/5/9 ds20002197c-page 36 ? 2009-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2014 microchip technology inc. ds20002197c-page 37 mcp631/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp631/2/3/4/5/9 ds20002197c-page 38 ? 2009-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2014 microchip technology inc. ds20002197c-page 39 mcp631/2/3/4/5/9
mcp631/2/3/4/5/9 ds20002197c-page 40 ? 2009-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2014 microchip technology inc. ds20002197c-page 41 mcp631/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp631/2/3/4/5/9 ds20002197c-page 42 ? 2009-2014 microchip technology inc.
? 2009-2014 microchip technology inc. ds20002197c-page 43 mcp631/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp631/2/3/4/5/9 ds20002197c-page 44 ? 2009-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2014 microchip technology inc. ds20002197c-page 45 mcp631/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp631/2/3/4/5/9 ds20002197c-page 46 ? 2009-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging un
? 2009-2014 microchip technology inc. ds20002197c-page 47 mcp631/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging un
mcp631/2/3/4/5/9 ds20002197c-page 48 ? 2009-2014 microchip technology inc. 10-lead plastic micro small outline package (un) [msop] note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2014 microchip technology inc. ds20002197c-page 49 mcp631/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp631/2/3/4/5/9 ds20002197c-page 50 ? 2009-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2014 microchip technology inc. ds20002197c-page 51 mcp631/2/3/4/5/9
mcp631/2/3/4/5/9 ds20002197c-page 52 ? 2009-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2014 microchip technology inc. ds20002197c-page 53 mcp631/2/3/4/5/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
mcp631/2/3/4/5/9 ds20002197c-page 54 ? 2009-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2014 microchip technology inc. ds20002197c-page 55 mcp631/2/3/4/5/9 d e n 2 1 exposed pad d2 e2 2 1 e b k n note 1 a3 a1 a l top view bottom view
mcp631/2/3/4/5/9 ds20002197c-page 56 ? 2009-2014 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2009-2014 microchip technology inc. ds20002197c-page 57 mcp631/2/3/4/5/9 appendix a: revision history revision c (july 2014) the following is the list of modifications: 1. updated the features: list. 2. added the high gain-bandwidth op amp portfolio table in the features: section. 3. updated figures 4-6 and 4-11 . 4. updated section 6.0 ?packaging information? and section 6.1 ?package marking information? . 5. minor typographical changes. revision b (november 2011) the following is the list of modifications: 1. added the mcp634 and mcp639 amplifiers to the product family and the related information throughout the document. 2. added the 2x3 tdfn (8l), sot23 (5l) package option for mcp631, sot23 (6l) package option for mcp633, 4x4 qfn (16l) package option for mcp639, soic and tssop (14l) package options for mcp634 and the related information throughout the document. updated package types drawing with pin designation for each new package. 3. updated the temperature specifications table to show the temperature specifications for new packages. 4. updated ta b l e 3 - 1 to show all the pin functions. 5. updated section 6.0 ?packaging informa- tion? with markings for the new additions. added the corresponding sot23 (5l), sot23 (6l), tdfn (8l), soic, tssop (14l), and 4x4 qfn (16l) package options and related infor- mation. 6. updated table description and examples in the product identification system section. revision a (august 2009) ? original release of this document.
mcp631/2/3/4/5/9 ds20002197c-page 58 ? 2009-2014 microchip technology inc. product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. -x /xx package temperature range device device: mcp631 single op amp mcp631t single op amp (tape and reel) (soic, sot-23, tdfn) mcp632 dual op amp mcp632t dual op amp (tape and reel) (dfn and soic) mcp633 single op amp with cs mcp633t single op amp with cs (tape and reel) (soic, sot-23) mcp634 quad op amp mcp634t quad op amp (tape and reel) (tssop and soic) mcp635 dual op amp with cs mcp635t dual op amp with cs (tape and reel) (dfn and msop) mcp639 quad op amp mcp639t quad op amp (tape and reel) (qfn) temperature range: e = -40c to +125c package: ot = plastic small outline (sot-23), 5-lead chy = plastic small outline (sot-23), 6-lead mny= plastic dual flat, no lead (2x3 tdfn), 8-lead mf = plastic dual flat, no lead (33 dfn), 8-lead, 10-lead sn = plastic small outline (3.90 mm), 8-lead un = plastic micro small outline (msop), 10-lead sl = plastic small outline, narrow, (3.90 mm soic), 14-lead st = plastic thin shrink small outline, (4.4 mm tssop), 14-lead ml = plastic quad flat, no lead package (4x4 qfn), (4x4x0.9 mm), 16-lead examples: a) mcp631t-e/ot: tape and reel extended temperature, 5ld sot-23 package b) mcp631t-e/mny:tape and reel extended temperature, 8ld tdfn package c) mcp631t-e/sn: tape and reel extended temperature, 8ld soic package d) mcp632t-e/mf: tape and reel extended temperature, 8ld dfn package e) mcp632t-e/sn: tape and reel extended temperature, 8ld soic package f) mcp633t-e/sn: tape and reel extended temperature, 8ld soic package g) mcp633t-e/chy: tape and reel extended temperature, 6ld sot package h) mcp634t-e/sl: tape and reel extended temperature, 14ld soic package i) mcp634t-e/st: tape and reel extended temperature, 14ld tssop package j) mcp635t-e/mf: tape and reel extended temperature, 10ld dfn package k) mcp635t-e/un: tape and reel extended temperature, 10ld msop package l) mcp639t-e/ml: tape and reel extended temperature, 16ld qfn package.
? 2009-2014 microchip technology inc. ds20002197c-page 59 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2009-2014, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63276-382-2 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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